`timescale 1ns/1ps

module DDS_AD9767_tb;

	reg 			clk	;
	reg 			rst_n	;
	reg			key	;
	wire [13:0]	data_A;
	wire 			clk_A	;
	wire 			WRTA	;
	wire [13:0]	data_B;
	wire 			clk_B	;
	wire 			WRTB	;
 
	DDS_AD9767 DDS_AD9767(
		.clk		(clk		),
		.rst_n	(rst_n	),
		.key		(key		),
		.data_A	(data_A	),
		.clk_A	(clk_A	),
		.WRTA		(WRTA		),
		.data_B	(data_B	),
		.clk_B	(clk_B	),
		.WRTB		(WRTB		)
	);
	
	initial clk = 1;
	always #10 clk = !clk;
	
	initial begin
		rst_n = 0;
		key = 0;
		#201;
		rst_n = 1;
		#2000000;
		$stop;
	end

endmodule 